The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A bonded wafer stack includes two wafer stacks bonded together via bonding layers. Each of the wafer stacks may include semiconductor wafers that are stacked during fabrication and a bonding (metal) layer. Each semiconductor wafer may include one or more integrated circuits (ICs) with respective electronic components. A top surface of the bonded wafer stack may be electroplated during fabrication. In order to electroplate the top surface, a seed layer is applied to the top surface prior to electroplating. The seed layer allows electroplating material (or a metal layer) to be attached to the top surface.
The seed layer is applied across the top surface and over peripheral edges of a first (top) one of the wafer stacks. Electroplating pins are connected to the seed layer proximate the peripheral edges to supply current to the seed layer during electroplating. Electroplating requires a conductive path from the electroplating pins at the peripheral edges to all regions of the top surface of the wafer stack.
The seed layer can have discontinuities (or gaps) along the peripheral edges of the bonded wafer stack. The discontinuities can be due to the shape (sharp corners) of the peripheral edges and/or due to overhang areas of one or more layers of the bonded wafer stack. For example, the first one of the two wafer stacks may be larger than and extend over (i.e. overhang) a first bonding layer in an overhang area. The first bonding layer may be disposed between and used to bond the two wafer stacks. The seed layer may be applied over the first wafer stack and over the overhang area. The sharp edges of the first wafer stack and the overhang area can result in discontinuities in the seed layer.
The discontinuities can negatively affect thickness uniformity of an electroplate layer that is formed across the top surface of the bonded wafer stack during the electroplating process. Thicknesses of the electroplate layer are a function of the conductivities and/or resistances of the seed layer. The larger the discontinuities and/or the more discontinuities that exist in the seed layer, the more the thickness of the electroplate layer varies across the top surface of the bonded wafer stack.
Resistances between a center of the top surface of the bonded wafer stack and the electroplating pins can vary, for example, between tens to hundreds of ohms. This variance in resistance can result in electroplate layer thickness non-uniformity, depending upon the average electroplate layer thickness.